Team Demonstrates Room Temperature ALD and Etching

A University of Colorado, Boulder (CU) team recently devised a new method for room temperature ALD. They created the procedure known as electron-enhanced atomic layer deposition (EE-ALD), as part of DARPA’s Local Control of Materials Synthesis (LoCo) program. The CU team proved room-temperature deposition for both silicon and gallium nitride, key elements in advanced microelectronics.

Gallium Nitride film deposited on a Silicon substrate at 27 degrees Celsius (80 degrees Fahrenheit) using EE-ALD process. (University of Colorado Boulder image)

Gallium Nitride film deposited on a Silicon substrate at 27 degrees Celsius (80 degrees Fahrenheit) using EE-ALD process. (University of Colorado Boulder image)

The team also demonstrated the ability to etch certain materials at room temperature. The team says that the new etching method in combination with the deposition method would lead to precise spatial control in three dimensions. After first performing the process in early 2015, team members went on to conduct detailed mechanistic studies to find out how to best exploit and control EE-ALD film growth. Controlling the electron energy during the ALD cycles, enabled the team to tune the process to favor either material deposition or removal (etching).

The group is also testing other methods to etch specific materials including aluminum nitride and hafnium oxide.
They intend to show that they can selectively etch these materials in composites. Room temperature composite etching could provide an attractive alternative to traditional masking approaches.

CU has also constructed a custom deposition chamber to demonstrate industrial relevance and scalability of the EE-ALD process.
The chamber can deposit or etch films composed of multiple materials on industrial-scale six-inch silicon wafers.

The researchers are now attempting to understand the EE-ALD process to better control the fabricated film’s composition and properties in three dimensions.

“Looking forward, the EE-ALD approach could serve not just as a tool for integrating incompatible materials but also more generally to build and etch device architectures at atomic scales, an increasingly important capability as circuit geometries shrink,” said Tyler McQuade, DARPA program manager.

In principle, the procedure could be scaled to larger substrates and parallelized for processing many wafers at once.