Raytheon UK’s semiconductor business in Glenrothes, Scotland, UK together with researchers at Newcastle University, have commenced a Knowledge Transfer Partnership (KTP) project, to improve the performance of silicon carbide (SiC) electronic devices, specifically for use in Raytheon’s own SiC CMOS process. Innovate UK (formerly the Technology Strategy Board) supports the KTPs. Raytheon UK’s KTP with Newcastle University is examining the interface between SiC and silicon dioxide (SiO2), which critically impacts the performance of a metal-oxide-semiconductor field-effect transistor (MOSFET).
According to Raytheon, ‘Trap’ defects in the interface between the two materials affect the maximum current and threshold voltage that a MOSFET can handle. “Interface defects represent a significant obstacle in the mass adoption of silicon carbide technology in a wide range of sectors, such as aerospace, automotive, rail and energy, in which increasingly high-performance devices are required,” said John Kennedy, head of Raytheon UK’s Integrated Power Solutions.
Raytheon UK asserts that a full understanding of the interface behavior will enable it to optimize its manufacturing processes to minimize the occurrence of traps that reduce device performance. At the European Conference on Silicon Carbide and Related Materials (ECSCRM 2014) in Grenoble, France (21-25 September), Raytheon and New Castle plan to present their interim findings of the KTP project, and other high-temperature SiC CMOS integrated circuit studies.