Germanium FETs with Smallest Nanowire and Gate Length Showcased

Imec unveiled new process improvements for the fabrication of next-generation devices at this week’s 2017 Symposia on VLSI Technology and Circuits in Kyoto, Japan.In addition, the research center says it has significantly improved the device performance and electrostatic control of high-pressure annealing (HPA) for both strained germanium p-channel FinFET and GAA devices.

Imec showcases germanium FET with nanowire diameter of 9nm and gate length of 40 nm

Imec showcases germanium FET with nanowire diameter of 9nm and gate length of 40 nm

For some time, the higher intrinsic carrier mobility of germanium and III-V materials have made researchers look to the materials as potential solutions for deeply scaled devices. However, such materials have a larger permittivity and a narrower bandgap than silicon. According to Imec, the larger permittivity and narrower bandgap of such materials makes it more difficult create designs with the necessary electrostatic control at scaled gate lengths. Imec says that new device architectures are needed to mitigate the electrostatic control issue.

In this respect, Imec’s results demonstrate significant improvements in electrostatic control for both strained germanium p-channel FinFET and gate all around (GAA) devices.

Nadine Collaert, Distinguished Member of Technical Staff at Imec, says that her team “adapted the process flow of our previously published 14/16nm-node strained germanium p-finFETs to study the benefit of strained germanium GAA p-FETs at short gate lengths and sub-10nm diameter.”

The team was able to process GAA p-FETs with the smallest nanowire diameter (d=9nm) and the shortest gate lengths (LG=40nm) reported to date.

At these minute gate lengths, Imec says the devices were able to maintain excellent electrostatic control with a drain-induced barrier lowering of 30mV/V and a sub-threshold slope of 79mV/dec.