Semiconductor Research Corporation and Stanford University Demonstrate Top-Gated FETs and CMOS Inverters
Source/Type: Reported News

Author: CompoundSemi News Staff

December 7, 2009... Stanford University, Semiconductor Research Corporation (SRC), and Taiwan Semiconductor Manufacturing Company have developed what they claim is the first top-gated field effect transistor (FETs) and CMOS inverters. The FETs and CMOS inverters feature 20 nanometer (nm) contact holes using diblock copolymer lithography. The researchers assert that this advance could eventually enable production of smaller, faster, and cheaper devices.

Thus far, feature sizes beyond the 22nm node have not been achieved. In recent years, researchers have begun to look at block copolymers because a thin film of it, under the right conditions, can self-assemble into regular arrays of holes on the order of 20nm or smaller in diameter. This tiny, self-assembled swiss cheese of block copolymer can act as a stencil for creating electrical contacts to very small semiconductor devices. Previous attempts at using self assembling block polymers have failed because the self-assembled holes were not aligned to existing features. However the SRC-sponsored work has produced functional devices and circuits employing diblock copolymer patterning for sub-22nm CMOS technologies on a full wafer scale.

“We believe this development will help to bring self-assembly closer to broad application in the semiconductor industry," commented H.-S. Philip Wong, a professor of Electrical Engineering at Stanford University.

The researchers hope to integrate the innovations into manufacturing processes in the next seven to ten years. The findings will be presented at IEEE’s 2009 International Electron Devices Meeting in Baltimore, Md., on December 9. Semiconductor Research Corporation News Release

See the Current Industry News Summary
See this article in its orginal context, with the other current news from the same week