Bilkent University Develops Process to Fabricate GaN TFTs at 200°C

Researchers from Bilkent University develop process to fabricate GaN TFT at low temperature

A team at Bilkent University in Turkey has developed a low-temperature process to fabricate gallium nitride (GaN) back-gated thin-film transistors (TFTs) on flexible and rigid substrates. They reported their findings in Applied Physics Letters. [S. Bolat et al, Appl. Phys. Lett., vol109, p233504, 2016].

The team was able to produce the GaN thin-film transistors with temperatures below 200°C, which is the lowest reported temperature for fabricating GaN-based transistors ever reported. Conventional TFT circuits are rigid and require high temperatures for deposition and annealing.

While organic and metal oxide devices often suffer from reliability issues, the reliability of metal oxides such as zinc oxide can be enhanced with encapsulation. However, encapsulation adds to production complexity and cost. Normally fabrication of GaN devises requires deposition at about 1000°C, but other techniques including atomic layer deposition have been created with a much improved thermal budget.

While they admit, that the present results are not high performance, the team hopes that material process optimization could lead to III-nitride-based flexible electronics. The researchers produced GaN TFTs on rigid p-type silicon and flexible polyethylene naphthalate (PEN).

First, they used hollow-cathode plasma-assisted atomic layer deposition (ALD) at 200°C to create 77nm aluminium oxide (Al2O3) and 11nm GaN layers on a silicon dioxide layer. They cut patterned windows in the silicon dioxide to define the devices. The researchers employed electron-beam evaporation to apply the 200nm silicon dioxide layer directly on the rigid silicon substrates.

A 100nm aluminium layer formed a back-gate structure on which the silicon dioxide was applied for PEN substrates. p-silicon formed the back gate of the devices in the rigid silicon. On a flexible substrate, the TFT managed a reduced on/off ratio of 7×102, while giving a higher threshold voltage of +2.5V.

Under 10V stress they found an electric field of 1.3MV/cm in the gate oxide. Under the same conditions ZnO-based TFTs have a shift of 11V.